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| general description features ics9148-17 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium/pro tm 9148-17 rev g 4/27/00 pin configuration !"# $%$& '# ()*+$( !"#$%$& '# ()*+$( &(,-.+ /(0( +*%%*)$* 1 -2 $ 3 *% ! #*0 $%$& &(, #" 1 (4(+$3 *+ ''+*#+5*%% 1 (4(+$'( '+( 1*$(1 5 *##'+5 # ,( $%$& *6%('#( %$&)3$3$%( 7 8 '+!!#'% 9 *$&*5( ( *'+ %( *+'+ 48-pin ssop power groups 2-:! 2;<2< -=>?=>:! ; - :! 22; %31 ==$ ( -:! 2; =- =>:! ; @+( +*%%%7 ( ' 1 !>+'+)'$*()'+ a"( 5(+( *( *%%$%$& (4' ()1 "'5" (() #'$ $( 3 (# $"* +(%(+'# 3 '0'5")'11( (+ (1( (+$(1 (4(+$3#%' %3'+51*$ * ((0( +*%%3 (%($*6%(,'" #"1 (4(+$3 *+ ''+ (* ( '+$%)(1 '0,:-0;*+) a,(%b( $%$& a, (1( (+$( * (*b*'%*6%( (4*%"($ 3 *%1 (4(+$39+( 1 c*+)+( $%$&1 ( 9c'%'+d2 8!.8$(+( ),+ (*) ($ # #)%*'+ ()$( ( '*% 5 *##'+5 '+( 1*$(*%%, $"*+5'+51+$'+ $%$& 5 *#'+5*+)1 (4(+$3 (%($'+))''+*%%3"( )(b'$( #(( "( (+'# ,( 7 *6'%' *'+ ,"'$" (4' ( "* *+)$%$& 6( *6%(,'"'+# *1( ,( 7 '5") 'b(=>*+) 3 '$*%%3 b')( 5 (*( "*+2+ %(, *('+! %*) => 3 '$*%%3 b')(6(( "*+2+ %(, *('+! %*) ,"'%(#*'+*'+'+5 !d 8)3$3$%(a"(*+)*+) $%$& 3 '$*%%3 b')(6(( "*+! + %(, *( cpu_stop# pci_stop# pll2 pll1 spread spectrum 48mhz 24mhz ref (0:1) cpuclk (0:3) sdram (0:11) pciclk (0:4) pciclk_f x1 x2 xtal osc pci clock divder stop stop stop sdata sclk fs(0:2) mode cpu3.3#_2.5 control logic config. reg. agp(0:1) latch por pci_stop cpu_stop 2 4 12 5 5 3 /2 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ics9148-17 pin descriptions ! " # $ "% % & '' ()' # r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , ) 2 : 0 ( f e r 2 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 5 . 2 _ # 3 . 3 u p c 2 , 1 n i v 3 . 3 = w o l , u p c v 5 . 2 = h g i h . v 5 . 2 r o v 3 . 3 s i l d d v r e h t e h w s e t a c i d n i u p c 1 . t u p n i d e h c t a l . , 7 2 , 2 2 , 6 1 , 9 , 3 5 4 , 9 3 , 3 3 d n gr w p. d n u o r g 41 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c . 2 x m o r f r o t s i s e r 52 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c . ) f p 3 3 ( p a c 4 1 , 62 d d vr w pv 3 . 3 l a n i m o n , ) 4 : 0 ( k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 f _ k l c i c pt u ok c o l c i c p g n i n n u r e e r f 1 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 8 0 k l c i c pt u o. t u p t u o k c o l c i c p 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 3 1 , 2 1 , 1 1 , 0 1) 4 : 1 ( k l c i c pt u o. s t u p t u o k c o l c i c p 7 4 , 5 1) 1 : 0 ( p g at u o. 4 d d v y b d e r e w o p , s t u p t u o t r o p c i h p a r g d e c n a v d a 7 1 # p o t s _ u p c 1 n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 1 : 0 ( p g a d n a s k c o l c ) 3 : 0 ( k l c u p c s t l a h ) 0 = e d o m , e d o m e l i b o m n i ( w o l t u p n i 1 1 m a r d st u ot u p t u o k c o l c m a r d s 8 1 # p o t s _ i c p 1 n i w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 5 : 0 ( k l c i c p s t l a h ) 0 = e d o m , e d o m e l i b o m n i ( 0 1 m a r d st u ot u p t u o k c o l c m a r d s , 1 3 , 9 2 , 8 2 , 1 2 , 0 2 8 3 , 7 3 , 5 3 , 4 3 , 2 3 ) 9 : 0 ( m a r d st u o. s t u p t u o k c o l c m a r d s 6 3 , 0 3 , 9 13 d d vr w p , s k c o l c z h m 8 4 d n a z h m 4 2 , e r o c , ) 1 1 : 0 ( m a r d s r o f y l p p u s . v 3 . 3 l a n i m o n 3 2a t a d sn ir o f t u p n i a t a di 2 . t u p n i l a i r e s c 4 2k l c sn if o t u p n i k c o l ci 2 t u p n i c 5 2 z h m 4 2t u o. k c o l c t u p t u o z h m 4 2 e d o m 2 , 1 n i . e d o m e l i b o m = 0 , e d o m p o t k s e d = 1 , n i p t c e l e s n o i t c n u f 8 1 , 7 1 n i p . t u p n i d e h c t a l 6 2 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 4 4 , 3 4 , 1 4 , 0 4) 3 : 0 ( k l c u p ct u o. l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 2 4l d d vr w pl a n i m o n v 3 . 3 r o v 5 . 2 r e h t i e , ) 3 : 0 ( u p c r o f y l p p u s 6 41 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 8 44 d d vr w p) 1 : 0 ( p g a r o f y l p p u s ics9148-17 functionality 2-d 8 - d 8 d 8a-!e!f 3 *%:<2<;-222 5 . 2 _ # 3 . 3 u p c l e v e l t u p n i ) a t a d d e h c t a l ( r o f d e t c e l e s r e f f u b : t a n o i t a r e p o 1d d v v 5 . 2 0d d v v 3 . 3 cpu 3.3#_2.5v buffer selector for cpuclk drivers. power management functionality mode pin - power management input control 5 2 n i p , e d o m ) t u p n i d e h c t a l ( 7 1 n i p8 1 n i p 0 # p o t s _ u p c ) t u p n i ( # p o t s _ i c p ) t u p n i ( 1 1 1 m a r d s ) t u p t u o ( 0 1 m a r d s ) t u p t u o ( # p o t s _ u p c# p o t s _ i c p , p g a k l c u p c s t u p t u o k l c i c p ) 5 : 0 ( , f _ k l c i c p , f e r z h m 8 4 / 4 2 m a r d s d n a l a t s y r c c s o o c v 01 w o l d e p p o t sg n i n n u rg n i n n u rg n i n n u rg n i n n u r 11 g n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u r 10 g n i n n u rw o l d e p p o t sg n i n n u rg n i n n u rg n i n n u r 2 s f1 s f0 s f m a r d s , u p c ) z h m ( i c p ) z h m ( p g a ) z h m ( c i p a o i , f e r ) z h m ( 111 2 . 0 0 14 . 3 38 . 6 68 1 3 . 4 1 110 0 90 30 68 1 3 . 4 1 10 1 3 . 3 82 34 68 1 3 . 4 1 100 5 72 34 68 1 3 . 4 1 011 5 75 . 7 35 78 1 3 . 4 1 010 5 . 8 65 2 . 4 35 . 8 68 1 3 . 4 1 001 8 . 6 64 . 3 38 . 6 68 1 3 . 4 1 000 0 60 30 68 1 3 . 4 1 ics9148-17 2 a"( $%$&5(+( * ' * %*b( ($('b( $# +(+$*+ (*)6*$&"()** ()'+"(%*$"( 1 b( '1'$*'+ a"()** *+ 1( *( ()63"' $%$&5(+( * ' 2!!>6' ($ %( : *+)* )#)(; a"('+ ' ( *'+5*%5'$%(b(% a"()**63(1 #*' 6'63( a '# %'13"($%$&5(+( * '+( 1*$("( $%' ( (+%3g ! g1 #"($+ %%( a"( 63( # 6(*$$( ()'+ (4(+'*% )( 1 #%,( "'5"( 63(,'""(*6'%'3 *1( *+3$# %((63( "* 6((+ *+ 1( ()a"(##*+)$)(*+)c3($+ ",+*6b(# 6( (+6"()**' '5+ ()1 " ( ,63( a"()**' %*)()+'%* (4(+$(' ' () . ,( 7+*%% (5' ( * ( (*)(1*%$+)''+* ",+ general i 2 c serial interface information a"('+1 #*'+'+"' ($'+* #( 1*#'%'* '3,'" 5 *##'+5 # ('+1 #*'+$+*$ 1 *+ 5 *##'+5* %'$*'++( how to write: + %%( :" ; (+) * * 6' + %%( :" ; (+) "(, '(*)) ( $%$&,'%% + %%( :" ; (+) *)##3$##*+)$)( $%$&,'%% + %%( :" ; (+) *)##363($+ $%$&,'%% + %%( :" ; * (+)'+51' 63(:c3(!; " 5"63( $%$&,'%% (*$"63( + %%( :" ; (+) * 6' how to read: + %%( :" ;,'%% (+) * 6' + %%( :" ; (+) "( (*)*)) ( $%$&,'%% $%$&,'%% (+)"( + %%( :" ;*$&+,%()5( $%$& (+) 1' 63( + %%( :" ;,'%%+(()*$&+,%()5((*$"63( + %%( :" ;,'%% (+)* 6' controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write: " ics9148-17 # $% & # &' # ( )* + $, serial configuration command bitmap ' * *)(#* &1"'%' *'+ t i bn o i t p i r c s e dd w p 7 t i b n o i t a l u d o m m u r t c e p s d a e r p s % 5 . 1 - 0 n o i t a l u d o m m u r t c e p s d a e r p s % 6 . 0 - 1 0 t i b 4 : 6 4 , 5 , 6 t i b 1 1 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 k c o l c u p c 2 . 0 0 1 0 9 3 . 3 8 5 7 5 7 5 . 8 6 8 . 6 6 0 6 i c p 4 . 3 3 0 3 2 3 2 3 5 . 7 3 5 2 . 4 3 4 . 3 3 0 3 p g a 8 . 6 6 0 6 4 6 4 6 5 7 5 . 8 6 8 . 6 6 0 6 1 e t o n 0 , 0 , 0 3 t i b , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 s t u p n i d e h c t a l ) e v o b a ( 4 : 6 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 2 t i b . e p y t d a e r p s r e t n e c m u r t c e p s d a e r p s - 0 . e p y t d a e r p s n w o d m u r t c e p s d a e r p s - 1 0 1 t i b l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 0 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0 ' # # * " + , - . * # * . " " " * + , % # , - % h -,( 7 (1*% . ics9148-17 # % / 01 0 23 2 ( ) + 45 $ + 4, t i b# n i pd w pn o i t p i r c s e d 7 t i b8 21 ) t c a n i / t c a ( 7 m a r d s 6 t i b9 21 ) t c a n i / t c a ( 6 m a r d s 5 t i b1 31 ) t c a n i / t c a ( 5 m a r d s 4 t i b2 31 ) t c a n i / t c a ( 4 m a r d s 3 t i b4 31 ) t c a n i / t c a ( 3 m a r d s 2 t i b5 31 ) t c a n i / t c a ( 2 m a r d s 1 t i b7 31 ) t c a n i / t c a ( 1 m a r d s 0 t i b8 31 ) t c a n i / t c a ( 0 m a r d s # % / 01 0 23 2 ( ) + 45 $ + 4, # "% 6 0 23 2 ( ) + 45 $ + 4, - % 2+*$'b(#(*+ * ("(%)=9h*+)* ()' *6%() 1 # ,'$"'+5 =*$"() (4(+$3 (%($ ,'%%6(+b( ()%5'$%(b(%1 "('+ 1 (4(+$3 (%($ '+$+)''+ t i b# n i pd w pn o i t p i r c s e d 7 t i b-- # 0 s f d e h c t a l 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b7 11 ) t c a n i / t c a ( 1 1 m a r d s ) y l n o e d o m p o t k s e d ( 2 t i b8 11 ) t c a n i / t c a ( 0 1 m a r d s ) y l n o e d o m p o t k s e d ( 1 t i b0 21 ) t c a n i / t c a ( 9 m a r d s 0 t i b1 21 ) t c a n i / t c a ( 8 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-- # 2 s f d e h c t a l 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b7 41 ) t c a n i / t c a ( 1 p g a 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b6 41 ) t c a n i / t c a ( 1 f e r 0 t i b21 ) t c a n i / t c a ( 0 f e r # % 75 0 23 2 ( ) + 45 $ + 4, # % 0 23 2 ( ) + 45 $ + 4, t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 t i b n o i s r e v 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b0 41 ) t c a n i / t c a ( 3 k l c u p c 2 t i b1 41 ) t c a n i / t c a ( 2 k l c u p c 1 t i b3 41 ) t c a n i / t c a ( 1 k l c u p c 0 t i b4 41 ) t c a n i / t c a ( 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-- # 1 s f d e h c t a l 6 t i b71 ) t c a n i / t c a ( f _ k l c i c p 5 t i b5 11 ) t c a n i / t c a ( 0 p g a 4 t i b4 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b2 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b1 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b0 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b81 ) t c a n i / t c a ( 0 k l c i c p ics9148-17 cpu_stop# timing diagram ? a9i' *+* 3$" + '+ "($%$& 3+"( ' ( ' () +11"( $%$& 1 %, ,( ( *'+ ? a9i' 3+$" +' ()63"( a"(#'+'##"*"( $%$&' (+*6%(): ? a9i"'5" % (;' 2!! $%$& %%"( $%$& ,'%%$+'+( +,"'%("( $%$& * ()' *6%()a"( $%$& ,'%%*%,*3 6( ()'+ *%, *(*+) * '+ $"*#*++( "*5* *+(( "("'5" % (,')"' *1%% % ( $%$&+%*(+$3' %( "*+ $%$& *+) $%$&11%*(+$3' %( "*+ $%$& / % " 0 $ 1 0 $2345 6 , " %* %, 7 4" , "8 " 0 $ 1 " 039: ; / " 1 7 0 $ /( 1 * ics9148-17 pci_stop# timing diagram ? a9i' *+* 3+$" + '+ "( ' () +11"(=>:! ;$%$& 1 %, ,( ( *'+ ? a9i' 3+$" +' ()63"( '+( +*%%3a"(#'+'##"*"(=>:! ;$%$& * ((+*6%():? a9i "'5" % (;' *%(* 2!=>:! ;$%$& =>:! ;$%$& * ( ()'+*%, *(*+) * (),'"*1%%"'5" % ( ,')"5* *+(()=>:! ;$%$&+%*(+$3$3$%( * (+%3+( ' '+5=>$%$&11%*(+$3' +(=>$%$& cpuclk (internal) pciclk (internal) pciclk (free-running) cpu_stop# (high) pciclk (external) pci_stop# / % " 0 $0< = " 039: ! > 02345 6 , " %* %, 7 4" + * , "8 " 039: / " 1 * ics9148-17 fig. 1 shared pin operation - input/output pins a"(9 '+ )( '5+*()63:'+ ;+"( j272e ( b(* )*% '5+*%1+$'+ "()(b'$( '+5'+''*% ,( 7 "(3*$* '+ '+ a"(%5'$%(b(%:b%*5(; "*' ( (++"( ( '+ *"' '#(' (*)*+) () '+* 76''+( +*%)**%*$""((+)1,( 79+ ( ( : (($"* *$( ' '$ 1 '#'+5b*%( ;"()(b'$($"*+5( "(#)(1 ( *'+ 1 "( ( '+ *+ 1+$'+ +"' #)("( '+ )$("( ($'1'()611( ()$%$& (0( +*%%*) a 5 *#:%*);"('+( +*%$+1'5 *'+ (5' ( 1 "( ( '+ * ( ' ' $++($()('"( "( :%5'$2; ,( %3 "(/ :%5'$!;b%*5( (+'*%2!>'%"# :2!>; ( ' ' () b')( 6" "( %') 9 5 *##'+5 b%*5( +(()() ) '+5 "( ,( 7 5 *##'+5 ( ')*+) b')(*+'+ '5+'1'$*+%*)+ "( $%$&) '+5"( 6 (4(+ ( *'+5 ( ') via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k '5 (2 ", *#(*+ 1'# %(#(+'+5"' 1+$'+,"(+ * ,'$" '+"(*)( ' ()h'"+k# ( ' '+ *%%() "( '+,'%%6( %%()"'5"h'""(k# ( '+ %*$("( '+ ,'%%6( %%()%,1 5 *##*6'%'3' ++($( * 3"*+ +%3* '+5%( ( ' ' +($( * 3a"( 5 *##'+5 ( ' "%)6(%$*()$% ("( ( '( ( #'+*'+ ( ' #'+'#' ("($ (+% * (*' # ('# *+%$*( "( ( '( ( #'+*'+ ( ' $% ("() 'b( "*+"( 5 *##'+5 ( ' $ ics9148-17 absolute maximum ratings %3%*5( e! =5'$+ / l! m! #6'(+9 ( *'+5a(# ( * ( !fme!f *5(a(# ( * ( l. fm2 !f ( ( *6b(" (%' ()+)( #*3$* ( ( #*+(+)*#*5("()(b'$(a"( ( *'+5 * ( ( ($'1'$*'+ +%3*+)1+$'+*% ( *'+1"()(b'$(*"( ( *+3"( $+)''+ *6b(" (%' ()'+"( ( *'+*% ($'+ 1"( ($'1'$*'+ ' +'# %'()0 (*6 %(#*0'## *'+5$+)''+ 1 (0(+)() ( ') #*3*11($ )$ (%'*6'%'3 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a operating i dd3.3op c l = 0 pf; 66.8 mhz 100 160 ma supply current input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 2 ms settling time 1 t s from 1st crossing to 1% target freq. ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 2 ms skew 1 t cpu-sdram1 v t = 1.5 v; sdram leads -500 200 500 ps t cpu-pci1 v t = 1.5 v; cpu leads 256ns 1 guaranteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op c l = 0 pf; 66.8 mhz 10 20 ma supply current t cpu-sdram2 v t = 1.5 v; v tl = 1.25 v; sdram leads -500 200 500 ps t cpu-pci2 v t = 1.5 v; v tl = 1.25 v; cpu leads 256ns 1 guaranteed by design, not 100% tested in production. skew 1 ics9148-17 electrical characteristics - cpu t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 a i oh = -28 ma 2.5 2.6 v output low voltage v ol2a i ol = 27 ma 0.35 0.4 v output high current i oh2 a v oh = 2.0 v -29 -23 ma output low current i ol2 a v ol = 0.8 v 33 37 ma rise time t r2a 1 v ol = 0.4 v, v oh = 2.4 v 1.75 2 ns fall time t f2a 1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle d t2a 1 v t = 1.5 v 45 50 55 % skew t sk2a 1 v t = 1.5 v 50 250 ps jitter, one sigma t j1s2a 1 v t = 1.5 v 65 150 ps jitter, absolute t jabs2a 1 v t = 1.5 v -250 165 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage voh2b i oh = -8 ma 2 2.2 v output low voltage vol2b i ol = 12 ma 0.3 0.4 v output high current ioh2b v oh = 1.7 v -20 -16 ma output low current iol2b v ol = 0.7 v 19 26 ma rise time tr2b 1 v ol = 0.4 v, v oh = 2.0 v 1.5 1.8 ns fall time tf2b 1 v oh = 2.0 v, v ol = 0.4 v 1.6 1.8 ns duty cycle dt2b 1 v t = 1.25 v 40 47 55 % skew tsk2b 1 v t = 1.25 v 60 250 ps jitter, single edge displacement 2 tjsed2b 1 v t = 1.25 v 200 250 ps jitter, one sigma tj1s2b 1 v t = 1.25 v 65 150 ps jitter, absolute tjabs2b 1 v t = 1.25 v -300 160 300 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. ics9148-17 electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.8 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.6 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 130 250 ps jitter, one sigma 1 t j1s1a v t = 1.5 v, synchronous 40 150 ps t j1s1b v t = 1.5 v, asynchronous 200 250 ps jitter, absolute 1 tab s1a v t = 1.5 v, synchronous -250 135 250 ps t jabs1b v t = 1.5 v, asynchronous -650 500 650 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.75 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.5 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 200 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 50 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v (with synchronous pci) -250 +250 ps jitter, absolute 1 t jabs1 v t = 1.5 v (with asynchronous pci) -400 400 ps 1 guaranteed by design, not 100% tested in production. ics9148-17 electrical characteristics - agp t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.1 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns duty cycle d t1 1 v t = 1.4 v 45 49 55 % skew t sk1 1 v t = 1.5 v 130 250 ps jitter, one sigma 1 t j 1s1 v t = 1.5 v 2 3 % jitter, absolute 1 t abs1a v t = 1.5 v, synchronous -5 2.5 5 % t jabs1b v t = 1.5 v, asynchronous -6 4.5 6 % 1 guaranteed by design, not 100% tested in production. electrical characteristics - 24mhz, 48mhz, ref0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 2.6 v output low voltage v ol5 i ol = 9 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 25 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 2 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.9 4 ns duty cycle d t5 1 v t = 1.5 v 455457% jitter, one sigma t j1s5 1 v t = 1.5 v 1 3 % jitter, absolute t jabs5 1 v t = 1.5 v -5 - 5 % 1 guaranteed by design, not 100% tested in production. ics9148-17 8 9# % 2; (*5 +) %*+(+"( %*3( 1"(c'+*%%* (* + ()63 *$( ;*&(*%% ,( *$( *+)b'* * ,')(* '6%(%,( '+)$*+$( - % 2%%$%$& "%)"*b( ( '( ( #'+*'+5 ( ' / ",+'+*%% %*$( '# b( (*)'6'%'3 1 )'*5 *# 9 '+*% $* *$' "%) 6( ()+*%% *+) 9 '+*%$ 3 *%%*)$* *$' * ( ($##(+)() :% 2 3 *%%*)b*%( )(( #'+()63 ( 2!! $( *#'$ %%+#* &()$* *$' * (!!2n$( *#'$ " ics9148-17 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9148 y f-17-t ! " #$ ?@335 2 /( :,'%%+$ (%*(,'")** "(( (b' '+; % #$ & " ' 03 / @ 3 '! 0*# %( ics xxxx y f - ppp - t |
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